Conference paper

Designing HFPGA-based Mealy FSMs with Transformation of Output Functions

K. Mielcarek, A. Barkalov, L. Titarenko (Univ. Zielona Gora, Poland)

A design method is proposed for LUT-based Mealy FSMs. The method is based on transformation of state codes into outputs of FSMs. Example of design and results of investigations are given. The method allows obtaining FSM logic circuits with less amount of LUTs than known from literature methods.

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Receipt of papers:

March 15th, 2024

Notification of acceptance:

April 30th, 2024

Registration opening:

May 1st, 2024

Final paper versions:

May 15th, 2024