Conference paper

Variability-Aware Table-Based DC Model of a Dual-Gate Transistor

D. Kasprowicz (Warsaw Univ. of Techn., Poland)

This paper presents a variability-aware table-based model of a transistor. It is shown to accurately capture its transfer curves in the presence of multiple geometry variations. The model has been successfully applied to the VeSFET – a transistor with two independent gates.

Download one page abstract

Receipt of papers:

March 15th, 2024

Notification of acceptance:

April 30th, 2024

Registration opening:

May 1st, 2024

Final paper versions:

May 15th, 2024