Conference paper

A Novel APS Pixel Level Rearrangement to Increase the Fill Factor and SNR in 0.35µm CMOS Technology

A. Baradaranrezaeii, F. Noruzpur, S. Mahdavi (Urmia Graduate Inst., Iran)

This paper presents a novel rearrangement in an APS pixel architecture that reduces the number of metal connections delivered to the pixel. Employing four instead of five different metals, the fill factor is increased about 24% respectively, preserving other characteristics such as pixel area, power consumption the same as the conventional APS structures. Moreover, as the mathematical calculations and simulation results prove that the signal to noise ratio is improved as a side effect of this idea considerably. Utilizing the proposed idea, the introduced noise through the select switch is shrunk down about 26dB as well as the readout mechanism. Meanwhile, the power supply noise is almost rejected. The structure has been designed in a typical 0.35µm CMOS process with a power supply of 3.3V and simulated by HSPICE using level 49 parameters software.

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Receipt of papers:

March 15th, 2024

Notification of acceptance:

April 30th, 2024

Registration opening:

May 1st, 2024

Final paper versions:

May 15th, 2024