A Method to Manage Unknown Values Generation and Propagation During Gate Level Simulations of Multi-Clock Digital Circuits

A. Łuczyk (Warsaw Univ. of Techn., Poland)

The paper presents a method for unknown signal values generation and propagation management during gate level digital simulations of multi-clock circuits. Unknown values occur at outputs of clock domain boundary flip-flops and latches when their timing parameters are violated by input signals and clocks. The method is based on gate level Verilog circuit model transformations. The transformation do not changes normal logic behaviour of the~circuit but influences it only in case of timing violation. The source of a timing violation information for the method are Verilog macro functions used in standard cells library files to describe timing constraints of a particular flip-flop or latch model. Proposed method is general, flexible and able to cope with the challenges in the design process of digital multi-clock and asynchronous circuits posed by today's nanometer technologies.