A 2nd-order ∆ΣAD Modulator Using Ring Amplifier and SAR Quantizer with Simplified Operation Mode

C. Pan, H. San, T. Shibata (Tokyo City Univ., Japan)

A 2nd-order ∆ΣAD modulator architecture is proposed to simplify the operation mode using ring amplifier and SAR quantizer. Proposed modulator architecture can guarantee the reset time for ring amplifier and relax the speed requirement on asynchronous SAR quantizer. The SPICE simulation results demonstrate the feasibility of the proposed 2nd-order modulator in 90nm CMOS technology. Simulated SNDR of 97.25dB is achieved while a sinusoid -1dBFS input is sampled at 25MS/s for the bandwidth is BW=195.3kHz. The power consumption of the analog part in the modulator is 1.5mW while the supply voltage is 1.2V.