A Highly Linear 4-bit DAC with 1GHz Sampling Rate Implemented in 28nm FD-SOI Process

Z. Jaworski (Warsaw Univ. of Techn., Poland)

This paper presents the design of capacitive divider based 4-bit DAC implemented in 28 nm FD-SOI process. The major goal of this project is not the DAC resolution itself but the converter linearity. In this particular design the integral and differential nonlinearity have to be as low as in case of 14-bit device. This objective imposes tough constrains on the design sensitivity to process variations. It turns out the threshold voltage of the transistors used in the switch is one of the important factors limiting the DAC linearity.