An Extendable Global Clock High-Speed Binary Counter Compatible with the FPGA CLBs

S. Kazeminia (Urmia Univ. of Techn., Iran), M. Ghafourzadeh, F. Noruzpur (Urmia Graduate Inst., Iran)

A low-power structure is proposed for high-speed global clock binary counters which can be simply used as an extendable structure inside the CLBs of FPGAs. Unit cell of the traditional local-clock binary counters is slightly modified to be firstly, implemented with global clock signal, and secondly, optimized in power consumption and area. The problems of generating local clock signal and related layout complexities are removed in ASIC design; also, a simple extendable structure is supposed for programmable devices in which global clock is only accessed. Simulation results, based on BSIM3v3 model of CMOS transistors in 0.18µm CMOS process, confirm that 12-bit counter based on the proposed structure consumes 2mW power at 2GHz operating frequency when 1.8Volts supply voltage is used. Number of transistors is reduced to 156 in 8-bit counter. Also, the unit cell could be implemented on Xilinx and Altera FPGAs without any modifications on CLB structure.