Performance Estimation of Lattice Boltzmann Method Implementation in ARUZ

G. Jabłoński, J. Kupis (Lodz Univ. of Techn., Poland)

The paper presents the performance estimation of D2Q9 Lattice Boltzmann method implementation on ARUZ, a massively parallel FPGA-based simulator built in Lodz, Poland in 2015. This machine, containing 25920 FPGAs has been optimized for execution of the Dynamic Lattice Liquid algorithm, however it can be also reconfigured for different purposes. The simulation of 864 x 384 lattice on 18 panels of ARUZ would reach the performance of 206 * 10^3 MLUPS (Million Lattice Updates per Second).