Comparator Design for Linearized Statistical Flash A-to-D Converter

T. Sugimoto, H. Tanimoto, S. Yoshizawa (Kitami Inst. of Techn., Japan)

We proposed a linearization technique with dynamic element matching for stochastic flash A-to-D converters (SFADCs), and estimated that 6-bit SFADC can be realized by using about 1,000 comparators through system level simulations. In this paper we present circuit level design of the linearized SFADC. First, we discuss the difference between requirements of comparators for conventional flash ADC and linearized SFADC. It was made clear that the offset voltage distribution for the comparators must have the same variance, within a required linear input range for proper linearization. Based on the considerations, we designed a comparator for 6-bit resolution of a linearized SFADC with 1 GHz sampling by using a standard 0.18 um CMOS process. The designed comparator has 15 uV sensitivity at 1 GHz sampling by simulation. Monte Carlo simulation of input offset voltage for the comparators indicated 63 mV standard deviation. Finally, 1,024 comparators are divided into 8 groups of 128 comparators, and applied the linearization technique within 580 mV of linear input range. The simulation results for 100 MHz 500 mVp-p input sine wave, 38 dB of spurious free dynamic range is achieved for 1 GHz sampling. This verifies the feasibility of 6-bit 1 GHz linearized SFADC.