Conference paper

The Future of CMOS: More Moore or The Next Big Thing?

W. Kuźmicz (Warsaw Univ. of Techn., Poland)

This paper discusses the industrial and research status of CMOS and CMOS-like commercial and emerging technologies. Effects of scaling on transistor cost, max. system complexity and performance are discussed. Performance of state-of-the-art CMOS VLSI systems is power-constrained. To discuss various existing and emerging technologies, a model of an abstract, technology-independent ideal switch is proposed. It is shown that in the power-constrained scenario the maximum performance (in terms of clock speed) is limited by the static Ioff current, and the Ion current (i.e. the current flowing when the device is switched on) is of secondary importance. CMOS and CMOS-like technologies: bulk CMOS, FDSOI, FinFET, tunnel FETs, junctionless FETs, nanowire FETs, and non-Si devices (e.g. carbon-based devices) are briefly presented and their technology readiness level is estimated. The main conclusion is that Si-based CMOS will remain the key VLSI technology for the next decade or longer, and older technology nodes (65 nm – 350 nm) will not be abandoned.

Download one page abstract

Receipt of papers:

March 15th, 2024

Notification of acceptance:

April 30th, 2024

Registration opening:

May 1st, 2024

Final paper versions:

May 15th, 2024