EIA/TIA-485 Transceiver in Standard 130 nm CMOS Technology

M. Wysocki, K. Siwiec, W. Pleskacz (Warsaw Univ. of Techn., Poland)

This paper describes the design of the transceiver, which is the implementation of the physical layer of EIA/TIA-485 standard. This circuit is a part of the more complex System on Chip, which is designed in 130 nm CMOS technology. The problems during the design process refer to the integration with this larger system. The biggest problem was the relatively high voltage, which may appear on the pins of the Integrated Circuit (IC) and destroy it. The challenge was not only to make the IC resistant to such high voltage but also to maintain the full functionality of the transceiver. Those issues forced to use circuit methods to minimalize the impact of this voltage. The troubles came up, when this high voltage issue have to be reconciled with the speci-fication of the standard. The design process, which include the development of the circuit methods is presented with the results.