Conference paper

FPGA Implementation of the Multiplication Operation in the Multiple-Precision Arithmetic

K. Rudnicki (Brightelligence Inc., UK), T. Stefanski (Gdansk Univ. of Techn., Poland)

Although standard 32/64-bit arithmetic is sufficient to solve most of the scientific-computing problems, there are still problems that require higher numerical precision. Multiple-precision arithmetic (MPA) libraries are software tools for emulation of computations in a user-defined precision. However, availability of a reconfigurable cards based on field-programmable gate arrays (FPGAs) in computing systems allows to implement MPA algorithms in hardware. Whereas addition and subtraction operations of two n-digit numbers require O(n) operations, the basecase multiplication is equivalent to the convolution computation that requires O(n^2) operations. Therefore, efficient implementation of the multiplication operation is crucial for application of the reconfigurable hardware in MPA computations. In this contribution, our implementation of the basecase-multiplication algorithm in MPA on FPGA is presented. The method is implemented using the very high speed integrated circuit hardware description language (VHDL) and benchmarked on Xilinx Artix-7 FPGA. In the developed implementation of the MPA multiplication, the multiplication of two integer 1024-bit numbers (2048-bit numbers) takes 205 nsec (819 nsec) with the use of 40 DSP modules. It gives 2-fold speedup in comparison to the reference results published in the literature.

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Receipt of papers:

March 15th, 2024

Notification of acceptance:

April 30th, 2024

Registration opening:

May 1st, 2024

Final paper versions:

May 15th, 2024