A High Precision Vernier Type Delta-Sigma Time to Digital Converter

K. Ando, T. Kato, S. Saikatsu, A. Yasuda (Hosei Univ, Japan)

In this paper, we propose a high precision vernier type delta-sigma time to digital converter (TDC) architecture. The time resolution of conventional delta-sigma TDC that has a delay stage consists of a delay element and three multiplexers is strongly dependent on the delay time for a delay element used in the delay stage and the measurement time. However, the delay time is limited by the complementary metal oxide semiconductor (CMOS) process and thus, the longer measurement time result in the longer operation time. To solve these problems, we introduce a new delay stage consisting of two delay elements and four multiplexers to the conventional delta-sigma TDC. Proposed delta-sigma TDC can relatively shorten the delay time and improve the time resolution compared with the conventional delta-sigma TDC. The effectiveness of the proposed method is confirmed by simulations using MATLAB/Simulink. When the delay time is reduced to one quarter as compared with the conventional delta-sigma TDC, the signal to noise ratio (SNR) of the proposed delta-sigma TDC is improved by 12.9dB.