An Analog Approach in the Implementation of the Digital Systems for High-Speed Applications

A. Baradaranrezaeii, M. Ghafourzadeh (Urmia Graduate Inst., Iran)

A mixed design, including a new analog approach is proposed for the implementation of the high-speed digital circuits and a full-adder is designed through the idea to show the advantages of the method. This means that an analog based current comparator is utilized as the main core of the proposed digital full-adder and a simple readout unit plays the role of a DFF as well. The full-adder with the corresponding DFF forms a synchronous digital block suitable for high-speed pipeline structures. The idea is applicable to every multi input digital blocks and both, the output and its complement can be generated simultaneously. The simulation results, through HSPICE software using level 49 parameters in 0.18µm standard CMOS technology, confirm the precise operation of the full-adder and the proposed idea consequently. Only 305µW power consumption is required at 4G operations per second in different process corners, introducing 100mV peak-to-peak power supply noise. Moreover, 8G operations per second are achievable in dual channel mode where each of which operates in clock signal and its complement respectively.