Design of High-Performance PFD-CP for 403MHz CMOS Fractional-N Frequency Synthesizer

S. Saleh, G. Hamdy, H. Elsemary, A. Zaki (Electronics Research Inst., Egypt)

This brief discusses the challenges and employs a novel charge-pump and a PFD/CP linearization technique to improve the performance of a 403MHz fractional-N PLL. Techniques are proposed to improve the linearity of the PLL by forcing the PFD/CP to operate in a linear part of its transfer characteristics, while the charge-pump minimizes the current mismatch between the up and down currents by using feedback. The circuit is designed in 0.13µm CMOS process and consumes a total power of 2.6mW. The simulation results show that the synthesizer has a phase noise of -128dBc/Hz at 1MHz offset.