Conference paper

Digitally-Assisted Analog-to-Digital Converters in Deep-Nanoscale CMOS

J. Goes (Univ. Nova de Lisboa, Portugal)

High resolution analog-to-digital converters (ADCs) with sampling rates in the range of 80 to 320 MS/s are required in high-quality imaging and modern digital communication systems. Low-voltage, low-power and low area solutions are of great importance in the design of these ADCs. For single battery operated systems, low power dissipation is necessary to ensure a reasonable battery lifetime. Finally, silicon area is of paramount importance since it is directly related with the cost of the integrated circuit (IC).

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Receipt of papers:

March 15th, 2024

Notification of acceptance:

April 30th, 2024

Registration opening:

May 1st, 2024

Final paper versions:

May 15th, 2024