Conference paper

Electrical Characterization of Different Types of Transistors Fabricated in VeSTIC Process

G. Głuszko, D. Tomaszewski, K. Domański (Institute of Electron Techn., Poland)

A development of the VeSTIC technology is reported. The manufacturing of the test structures with different types of transistors is described. The electrical I-V characteristics of the MOS and junction field effect transistors and of the bipolar junction transistors produced in VeSTIC technology were measured. Basic parameters of the test devices were extracted using the basic device compact models. The technology was assessed taking into consideration the process variability issues.

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Receipt of papers:

March 15th, 2024

Notification of acceptance:

April 30th, 2024

Registration opening:

May 1st, 2024

Final paper versions:

May 15th, 2024