Conference paper

FOSS Compact Model Prototyping with Verilog-A Equation-Defined Devices (VAEDD)

M. Brinson (London Metropolitan Univ., UK)

Equation-Defined Device models (EDD) have become very popular for behavioural modelling of semiconductor and other non-linear devices. Two feature that makes them particularly attractive are their interactive nature and easy testing during the model development process. However, they are less suited for operation as production level models due to their slow simulation performance. This paper presents a new extension to the EDD that offers C++ model performance coupled with the convenience of EDD modelling. The extended form of the EDD is called a Verilog-A EDD or VAEDD for short. It has the same structure as the standard EDD but is built around compiled Verilog-A module code, which in turn is translated to C++ code and dynamically linked to the main body of the simulator code. Essentially a VAEDD is a tiny Verilog-A module with a standardised internal code structure. To demonstrate the interactive approach to compact model building with VAEDD components the design and testing of a high power SiC Schottky barrier diode is included in the main body of the text.

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Receipt of papers:

February 29th, 2020

Notification of acceptance:

April 25th, 2020

Registration opening:

April 30th, 2020

Final paper versions:

May 15th, 2020