A Low Power, Low Chip Area, Two-stage Current-mode DAC Implemented in CMOS 130 nm Technology

J. Dalecki (UTP Univ. of Science and Techn., Poland), R. Długosz, T. Talaśka (UTP Univ. of Science and Techn. and Aptiv Services, Poland), G. Fischer (Innovations for High Performance Microelectronics, Germany)

The paper presents measurement results of a current mode digital-to-analog converter (DAC), implemented in the IHP CMOS 130~nm technology. The proposed two-stage DAC is composed of 10 branches, so theoretically 10 bits of the resolution may be obtained. The circuit is reconfigurable. This means that if smaller resolutions are sufficient, the user may select the branches that are used in data conversion. The measurements were carried-out using a programmable measurement setup, designed for this purpose, equipped with precise current sources. Five samples of the prototype chip were tested. The measurements were carried out for different values of particular parameters. The circuit has been designed as one of the components of a Successive Approximation Register (SAR) analog-to-digital converter (ADC). However, it can be used as a separate block also for other purposes. The chip area of the overall ADC does not exceed 0.01 mm2, with the DAC occupying 60 % of this area.