Conference paper

A Clock-Free 200MS/s 10-bit Time-Interleaved SAR ADC

C.-H. Kuo, Z.-J. Luo (National Taiwan Normal Univ., Taiwan)

In this paper, a clock-free 200-MS/s 10-bit time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) is proposed. The presented SAR ADC can generate required clock by itself while an active signal is asserted. In the presented TI structure, two SAR ADCs are alternated with entering sample and comparison phases by the control circuit, and thus the equivalent sample rate can be doubled. The presented ADC is simulated under TSMC 90nm 1P9M CMOS process. Under a supply voltage of 1.2-V and an equivalent sampling rate of 200-MS/s, the resulted SNDR of the proposed ADC is 58.94 dB, which is equivalent to the ENOB of 9.50-bit. The simulated DNL and INL are within 0.735 / -0.404 and 0.734 / -0.552, respectively.

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Receipt of papers:

February 29th, 2020

Notification of acceptance:

April 25th, 2020

Registration opening:

April 30th, 2020

Final paper versions:

May 15th, 2020