Conference paper

Continuous-Time Discriminator Designin in CMOS 28 nm Process

P. Kaczmarczyk, P. Kmon (AGH Univ. of Science and Techn., Poland)

This paper presents discriminator design in 28 nm CMOS process. The core of the discriminator is based on the Operational Transconductance Amplifier (OTA) supported by additional blocks for its main parameters improvement. The positive feedback and Negative Impedance Converter (NIC) are here verified. The article provides information on particular improvement blocks influence on the discriminator operation speed, its power consumption and area occupation. Finally, the new architecture is proposed showing more than six times speed improvement and consuming only 31% more power comparing to the standard discriminator architecture. Additionally, the proposed solution mitigates the problem of the discriminators time response susceptibility on the input signal level. The final circuit consumes 3.8 μW of power at 10 MHz operating frequency, occupies only a 15 μm2 of area and allows to operate with impulses of 1.25 GHz frequency.

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Receipt of papers:

February 29th, 2020

Notification of acceptance:

April 25th, 2020

Registration opening:

April 30th, 2020

Final paper versions:

May 15th, 2020