Synthesis of LUT-based Mealy FSMs with Two Levels of Logic

A. Barkalov, K. Mielcarek, L. Titarenko (Univ. Zielona Gora, Poland)

A method is proposed for decreasing hardware in FPGA-based Mealy FSMs. The method is based on transforming state codes into class codes. The class codes are generated by the second level of FSM circuit An example of synthesis is given. The results of investigations are shown.