IEEE EDS DL Mini-Colloquium

IEEE Region 8 (Europe, Middle East and Africa), ED Poland Chapter
"Nanoelectronics - Technology, Design, Modeling"

Date: June 26, 2019

Venue: Grand Hotel Rzeszów Sp. z o.o. ul. Kościuszki 9, 35-030 Rzeszów, Poland

Mini-Colloquium organized by ED Poland Chapter with collaboration of:
Gdynia Maritime University, Gdynia, Poland
Łukasiewicz Research Network - Instytut Technologii Elektronowej (Łukasiewicz-ITE), Warsaw, Poland
Department of Microelectronics and Computer Science, Lodz University of Technology, Lodz, Poland

https://eds.ieee.org/education/distinguished-lecturer-mini-colloquia-program?eid=603&m=10e18da593444dc0cb20a2f377717f95

8:25
Introduction

8:30-9:15
Lecturer: Prof. Shinichi Takagi (The University of Tokyo)
Title: Tunneling FET technology for ultra-low power logic applications
Abstract: Supply voltage reduction is an effective way in reducing the power consumption, which is one of the most important requirements in integrated systems. From this viewpoint, steep slope properties in Id-Vg characteristics and resulting lower sub-threshold swing than that in CMOS are strongly expected for future logic devices. A tunnel FET (TFET) is regarded as one of the most promising steep slope devices, because of the operation principle utilizing the overlap of the density-of-states, which can be free from the thermal distribution of carriers.
In this presentation, the critical issues, technical challenges and viable technologies of TFET using a variety of semiconductors such as Si, Ge and oxide semiconductors are addressed. Device engineering indispensable in improving the performance of TFETs is summarized with emphasis on the source junction formation technology and the optimal material design. The electrical characteristics of TFETs using Si and Ge homo junctions, Ge/strained SOI hetero-junctions and ZnO/(Si, Ge) hetero-junctions are presented as the viable examples.

9:25-10:10
Lecturer: Prof. Andrzej Strójwąs (PDF Solutions, Santa Clara, CA and Carnegie Mellon University, Pittsburgh, PA15213)
Title: New Product Introduction Challenges in the Bleeding Edge Technology Nodes
Abstract: Layout Design Rules have been scaled very aggressively to enable 7nm technology node without EUV. As a result, achieving acceptable performance interaction and yield in High Volume Manufacturing (HVM) has become an extremely challenging task. Systematic yield and parametric variabilities have become quite significant. New characterization techniques are necessary to identify the yield and reliability risks. In this lecture, I will present a comprehensive methodology and a full suite of process-design design interaction characterization techniques to enable cost-effective introduction of new products in the 7nm and below technologies.

10:20-11:05
Lecturer: Dr. Arkadiusz Malinowski (GlobalFoundries)
Title: Will FinFET era last only for 10 years? FinFET scaling challenges for next CMOS technology nodes
Abstract: Due to undesired effects called short channel effects planar technology runs out of steam when physical gate length goes below 30nm. To overcome those effects and extend life of Moore’s Law in 2011 Intel has introduced 3-D tri-gate (FinFET) transistor into high volume manufacturing for 22nm technology. Others had followed. TSMC introduced FinFET in 2013 for 16nm technology and GLOBALFOUDNRIES in 2015 for 14nm technology. FinFET era has begun and now it is in mainstream of CMOS technology manufacturing but how long this era will last? Precursor of multi-gate transistor, double-gate transistor, was firstly proposed by Sekigawa and Hayashi in 1984. Idea of multi-gate transistor as we know it right now, FinFET, was proposed by Hisamoto in 1998 followed by production in 2011. However, Intel’s 7nm technology planned for 2021 might be the end of FinFET era which is just 10 years after its beginning. Similarly to planar technology FinFET is running out of steam as well. Additionally FinFET scaling for next technology nodes is very challenging and facing many difficult issues. Those challenges are related to: metrology / inspection, lithography / overlay, integration / variability, cycle time and cost. During Mini-Colloquium key FinFET technology scaling issues will be explained and discussed.

11:15
Coffee break

11:35-12:20 Lecturer: Dr. Rajiv V. Joshi (DL, IBM Research Division Yorktown Heights, NY)
Title: Variability Aware design in nm era
Abstract: As the technology scales, process, voltage and temperature, variations (PVT) and model inaccuracies impact design yield. In this talk predictive analytical technique based on statistical analysis methodology targeting both memory and custom logic design applications is highlighted. The methodology hinges on Mixture Important Sampling (MIS) is 5-6 orders of magnitude faster than Monte Carlo and few orders compared to recent techniques. For advanced technologies, we extend the methodology to enable key features such as Front End of the Line (FEOL) and back end of the line (BEOL) parasitic extraction and TCAD for manufacturability for 16nm and below. This increases the statistical confidence in the functionality and operability of the system-on-chip as a whole. We present design case studies both in planar and non-planar technologies.
Also Reliability is a key concern for VLSI circuits especially so for latches and memories due to their small feature sizes. Particularly, for SRAM cell designs Bias Temperature Instability (BTI) effects have significant implications on functionality and performance. Here we propose through simulation and modeling an efficient statistical methodology to evaluate and minimize the aging of memory chips. Redundancy has been typically used to resolve failing parts at beginning of life. In this approach, we propose to use redundancy to repair critical parts that are most susceptible to aging, thereby optimizing end-of-life yield. Our methodology enables what would have been a very expensive and exhaustive hardware testing approach by identifying optimal repair corners via fast statistical simulations. The methodology takes into consideration reliability effects in the presence of random process variation. This in turn identifies critical repair parts for optimal yield and helps minimize the ever increasing field failure problem. .

12:30-13:15
Lecturer: Prof. Henryk M. Przewłocki (DL, Łukasiewicz Research Network - Instytut Technologii Elektronowej)
Title: Expanding the horizon of photoelectric investigations of the MIS system properties
Abstract: The fundamental property of any nanoelectronic material or system is its energy band diagram, which allows to predict its physical properties, potential applications and/or limitations. The most effective methods of band diagram determination are the photoelectric methods, which deserve therefore detailed theoretical analysis, as well as precisely controlled experimental procedures.
It is shown in this paper that the commonly accepted and currently applied theory (further called classical theory) of internal photoemission in the metal-insulator-semiconductor (MIS) system, which very well represents its experimental characteristics taken at high enough electric fields E, in the insulator, fails at low electric fields (usually for E<(104-105) V/cm), i.e. in the vicinity of the point where the photocurrent changes sign (I=0). This failure of the classical theory will be demonstrated by comparing the characteristics calculated using the classical theory with the experimental characteristics taken in the range of low electric fields in the insulator.
It was already shown some time ago, by the present author that this discrepancy results from the neglect of the diffusion currents, which become important at low electric fields in the insulator. In this paper the origin, the magnitude and the role of diffusion current in determination of the MIS system photoelectric characteristics at low electric fields in the insulator will be quantitatively analyzed.
The theory of the photocurrent vs. gate voltage characteristics, at different wavelengths of light illuminating the structure under test, with diffusion currents taken into account will be presented. It will be shown that characteristics calculated using this theory remain in good agreement with the relevant experimental characteristics. The ability to accurately predict these characteristics in the range of low electric fields opens the possibilities of developing new measurement methods of the MIS system crucial parameters. Two examples of such methods will be demonstrated.

13:25
Lunch

14:15-15:00
Lecturer: Prof. Marcelo Pavanello (DL) (DL, Centro Universitario FEI)
Title: Performance and modeling of Nanowire-based MOSFETs
Abstract: The talk begins with the context of nanometer size transistors with multiple gates, exploring the differences between double-gate, triple-gate and nanowire-based MOSFETs. The Junctionless Nanowire Transistors (JNTs) is introduced as one of the interesting alternatives for downscaling because of their relative process simplicity compared with inversion-mode nanowires. The excellent scaling properties of JNTs are presented as well as their peculiar conduction mechanisms. Then, the core analytical models developed for describing the static and dynamic behavior of Junctionless Nanowire Transistors (JNT) as a function of electrodes voltages will be presented. The Verilog-A version of these models is demonstrated as well, allowing SPICE simulation of circuits using JNTs

15:10-15:55
Lecturer: Dr. Farzan Jazaeri (EPFL)
Title: Cryogenic Electronics and Quantum Computing Architecture
Abstract: Quantum computing is attracting more and more the interest of industrial actors, not only “broad-interest” corporations like Google (A research effort from Google that aims to build quantum processors) and Microsoft (empowering the quantum revolution with a complete approach to quantum systems), but also companies more traditionally linked to the area of nanoelectronics and nanotechnology. Quantum computing is now widely regarded by many in academia, governments and industry to represent a major new frontier in information technology with the potential for a disruptive impact. Many major corporations around the world, motivated by significant progress at basic research level, have started to invest on quantum technology. As the scaling trend of CMOS transistors is reaching insurmountable physical limits, the electronic industry is increasingly facing the challenge of finding alternative development routes. A possible solution to this problem may be found in radically new ideas such as quantum computation. Quantum computers hold the promise to solve problems that are intractable even for the most powerful supercomputers. They process the information stored in quantum bits (qubits), which must be typically cooled to cryogenic temperature. Qubit relies on a spin degree of freedom of either electronic or nuclear nature which can hold a bit of quantum information for very long times. A variety of spin qubits in silicon have already been proposed and experimentally demonstrated in academic research laboratories.

16:05
Coffee break

16:25-17:10
Lecturer: Prof. Mike Brinson (London Metropolitan University)
Title: Equation-Defined template and synthesis driven compact modelling of semiconductor devices
Abstract: The rapid expansion in emerging semiconductor devices has led to the need for improved compact modelling and circuit simulation tools. In order to achieve wide spread acceptance of any new modelling tool it must be simple to use, generate device models that produce accurate simulation data, simulate at practical speeds, meet international hardware description language standards and be freely available to the compact modelling community. This presentation reports on current research that links Equation-Defined Device modelling with Verilog-A modules, driven by code templates and synthesis, which in turn result in an improved interactive modelling technique that can be employed to construct compact models that have a similar performance to compiled C++ code models. Throughout the talk a series of compact device models will be introduced to demonstrate the fundamentals and application of the new approach to compact device modelling.

17:20-18:05
Lecturer: Dr. W³adek Grabiński (DL, MOS-AK and GMC)
Title: FOSS tools for support of IC modeling and design with special emphasis on Verilog-A standardization
Abstract: Compact/SPICE models of circuit elements (passive, active, MEMS, RF) are essential to enable advanced IC design using nanoscaled semiconductor technologies. To explore all related interactions, we are discussing selected FOSS CAD tools along complete technology/design tool chain from nanascaled technology processes. New technology and device development will be illustrated by application examples of the FOSS TCAD tools: Cogenda TCAD and DEVSIM. Compact modeling will be highlighted by review topics related to its parameter extraction and standardization of the experimental and measurement data exchange formats. Finally, we will present FOSS CAD simulation and design tools: ngspice, Qucs, GnuCap, Xyce.

18:15
End of Mini-Colloquium

Receipt of papers:

February 29th, 2020

Notification of acceptance:

April 25th, 2020

Registration opening:

April 30th, 2020

Final paper versions:

May 15th, 2020