A New Ultra High Speed 5-2 Compressor with a New Structure

M. Ghasemzadeh (Urmia Univ., Iran), S. Mahdavi (Urmia Graduate Inst., Iran), A. Zokaei, K. Hadidi (Urmia Univ., Iran)

This paper devotes to a new 5-2 compressor designed according to a new architecture with a pure Glitchless output. A considerable increase in the speed of the operation is achieved by utilizing a new truth table, fast production of signals Cout1 and Cout2, optimum tuning of the width of the utilizing transistors, and eliminating the parasitic capacitances through merging the drain of transistors. Additionally, the number of transistors used in this architecture (44) is less than the recent 5-2 compressors. The proposed structure’s delay proved by the results of the simulations applied to Hspice software using standard TSMC 0.18µm CMOS technology is about 155ps.