Bulk Controlled Offset Cancellation Mechanism for Single-stage Latched Comparator

S. Kazeminia (Urmia Univ. of Techn., Iran), S. Mahdavi, R. Gholamnejad (Urmia Graduate Inst., Iran)

A reliable offset cancelation strategy is proposed for single-stage latched comparators by in turn domination of positive and negative feedback devices. Feedback type is cautiously swapped by small voltage variations on bulk terminals of PMOS devices. For offset cancellation, at first a reset switch removes the previously latched data on comparator’s outputs while the inputs are shorted together. Secondly, the sampled offset is dependably pre-amplified providing a finite gain in presence of slightly stronger negative feedback. The positive feedback cannot be dominated right after the reset phase because small voltage might be still remained across the switches. Thirdly, the loop gain is considerably increased by slightly dominating the positive feedback. Then the main comparison is similarly scheduled by identical controls on bulk terminals. Worst-Case simulation results confirms that the proposed comparator can detect 2mVolts input difference, at all corner conditions, in presence of 15mVolts offset voltage at 625MS/s comparison rate. The Monte-Carlo simulation results show that the standard deviation of the input referred offset is 0.35mV while the input offset is within the range of ±15mVolts. Power consumption is 1.2mW at 625MS/s comparison speed. Simulations are performed for all corner conditions using the BSIM3 model of a 0.18µm CMOS technology.