Encryption Using Reconfigurable Reversible Logic Gate and Its Simulation in FPGAs

M. Bryk, K. Gracki (Warsaw Univ. of Techn., Poland), P. Kerntopf (Univ. Lodz, Poland), M. Pawłowski, A. Skorupski (Warsaw Univ. of Techn., Poland)

Recently an approach to encryption/decryption based on using reversible logic circuits has been proposed. The reason for this proposal is that conventional microelectronic technologies are reaching its limits. On the other hand, reversible logic circuits can decrease energy dissipation theoretically to zero. This paper presents a solution to designing encryption schemes based entirely on reversible logic. In our solution a building block of an encryption scheme is a cascade of 4-input reversible gates. Each of these gates can be chosen to perform any 4-variable function. For this purpose a reconfigurable reversible gate has been proposed. The design of such a reconfigurable gate is presented built from standard reversible gates, namely NOT, CNOT, Toffoli and Fredkin gates. In the paper a complete scheme for encryption/decryption of 8-bit data is described using VHDL language and its quantum cost is calculated. Simulation and verification of this scheme in FPGAs conclude the paper.