Hardware-accelerated Reconstruction of Compressed Neural Signals Based on Inpainting

S. Schmale, H. Kesuma, H. Lange, J. Rust, B. Knoop, D. Peters-Drolshagen, S. Paul (Univ. Bremen, Germany)

In this paper the first low-latency architecture design and hardware implementation for structure-based inpainting to detect and complete isophotes in brain activity recording is presented. This novel mask-based compression and inpainting-based reconstruction methodology for correlated neural signals is especially important for the realization of implantable neural measurement systems (NMS) due to restrictions in terms of area and energy. The data compression is obtained by on/off controlling of the recording electrodes on implant side. The low-latency and parallel architecture design is based on a synchronous Moore-FSM for 16 bits inputs. It requires only 8 cycles to compute the inpainting-based detection and completion of isophotes. Because of the error-robust inpainting recovery procedure, small accuracy differences between the simulation and measurement results on a Xilinx DS312 Spartan-3E FPGA are negligible. The proposed hardware implementation on logical and physical 350nm CMOS reaches a clock frequency of 78.452 MHz, which leads to a throughput of 653766 parallel inpainting-based isophote computations per second.