Programmable Frequency Divider Based on Modified Accumulator Architecture

S. Akbari, M. Amirpour, M. Shahdad, E. Abaspour Sani, M.N. Azarmanesh (Urmia Univ., Iran)

In this letter, a new programmable frequency divider based on modified accumulator architecture is presented. The main purpose of modification is to clear the register’s value when accumulator overflows. This modification enables fully constant output frequency in comparison with direct digital synthesizer’s average frequency in a period of time. Due to all-digital blocks and circuitries that are utilized in proposed divider, experimental results are measured on Xilinx FPGA. Simulations are done with HSPICE software in 180nm TSMC CMOS process.