Digitally-assisted Offset Cancellation Technique for Open Loop Residue Amplifiers in High-resolution and High-speed ADCs

S. Kazeminia (Urmia Univ. of Techn., Iran), S. Mahdavi, K. Hadidi (Urmia Graduate Inst., Iran)

In this paper a digitally-assisted foreground-liked calibration technique is proposed for offset cancellation of the residue amplifiers in high-resolution analog-to-digital converters. Two amplifiers are used while are in turn corrected for offset error. When the first amplifier participates in residue amplification the second one is calibrated to be substituted in the main data path. Two analog comparators are used to decide accumulation with +1 or -1 step based on the offset direction, or stop the count process. The digital equivalent of the input offset is stored on a digital latch array and is translated to analog voltage using a 10-bit digital-to-analog converter. Counting treat of the accumulator is stopped when the loop enters to the lock state. Simulation results confirm that the input offset voltage of around 8mVolts is reduced to less than 20µVolts when the gain of the auxiliary amplifier is 60dB. The Monte-Carlo analysis shows that the input-referred offset is around 53µVolts at 1σ while was 4.8mVolts before cancellation. The remained offset is reduced to less than the half value of LSB amplitude in 14-bits ADC where the peak-to-peak range is 1600mVolts. Simulations are performed using the BSIM3 model of a 0.18µm CMOS technology.