Architecture and Design of a Bluetooth Low Energy Controller

P. Wiecha, M. Ciepłucha, P. Kłoczko, W. Pleskacz (Warsaw Univ. of Techn., Poland)

This paper describes the architecture and design of a Bluetooth Low Energy Controller. The designed controller consists of a hardware and software part. The hardware part consists of a link layer and a physical layer (analog radio), which is out of the scope of this work. Great emphasis was placed on minimizing hardware area and power consumption. Most of the complex and sequential functions were moved to the software Intermediate Layer introduced in this paper. Furthermore, Single Port RAM (SPRAM) was used to reduce the number of registers in the design. Flexibility was achieved by division of the hardware into two separate clock domains. Hardware part was designed using fully synthesizable Verilog HDL to simplify integration process into a System on Chip (SoC). In the proposed architecture the standard Bluetooth software stack may be used for the controller management. The controller architecture, implementation and verification strategies are described in this paper.