Contribution to Scaling of the Vertical Slit Field-Effect Transistor (VeSFET)

A. Pfitzner, B. Kowalska (Warsaw Univ. of Techn., Poland)

Junction-less twin-gate Vertical-Slit Field-Effect Transistor (VeSFET) is the elementary component of a new 3D VeSTIC technology. Feasibility studies conducted until now indicate that VeSTIC architecture has the potential to overcome many barriers of ICs scaling in the deep-submicron era. As it was shown earlier, electrical properties of VeSFETs seems to be very attractive, but simulations indicate different correlations between electrical and structure parameters in comparison with those of MOSFETs operating in inversion mode. In this paper an exploration of the VeSFET parameters space has been developed and preliminary scaling recommendations are formulated.