Design of a Circuit for a CMRR Correction of Multichannel Integrated Circuits

P. Kmon, A. Lisicka (AGH Univ. of Science and Techn., Poland)

This paper presents a design of a circuit for Common Mode Rejection Ratio (CMRR) correction in Integrated Circuits (IC) dedicated to neurobiology experiments. The design is realized in CMOS 180nm process and will be adopted in an multichannel IC. Description of the design is preceded by CMRR measurement results of a former prototype IC where a novel CMRR correction method was adopted. A main requirement of the presented design was its ultra low power consumption, small area occupation and improved correction precision comparing to our former work. The paper also provides a review of solutions that aim at on-chip implementation of correction circuits used for channel-to-channel spread minimization of main IC’s parameters.