A Fault-tolerant Real-time Microcontroller with Multiprocessor Architecture

E. Strollo, A. Trifiletti (Univ. Rome Sapienza, Italy)

The occurrence of faults within microelectronic systems concern an increasing number of application fields. A possible way to build reliable systems is make them fault tolerant by the adoption of redundancies. In this paper we present the design and implementation of a fault tolerant microcontroller device using hardware redundancy of a multiprocessor. This system is FPGA based and parametrized, and can be configured to operate both as a multiprocessor or a single redundant processor, with three processors working in TMR and some spare processors. The indicated recovery procedure allows to rapidly correct transient faults, but also to replace the damaged processors after a permanent fault. The complete system employs three redundant processors on distinct boards, that are used in conjunction so as to have a further TMR level. In this way we obtain a module that is capable to solve all of the system faults, both at processor or boards levels. The programmable system is capable of masking faults, correcting errors, and also showing the possible gradual system degradation due to permanent faults.