Fast Integrated Circuit of Pixel Architecture for Digital X-ray Imaging

P. Gryboś, P. Kmon, P. Maj, R. Szczygieł (AGH Univ. of Science and Techn., Poland)

The UFXC32k integrated circuit designed in CMOS 130 nm process, contains about 50 million transistors in the area of 9.64 mm x 20.15 mm. The core of the IC is the matrix of 128 x 256 square shaped pixels of 75 µm pitch. Each pixel contains a charge sensitive amplifier, a shaper, a discriminator, correction circuits and two 14-bit counters. The data is read out via 8 Low Voltage Differential Signaling (LVDS) outputs. The UFXC32k chip is bump-bonded to a pixel silicon sensor and fully characterized in X-ray radiation. The measured equivalent noise charge is equal to 123 e- rms (for the peaking time of 40 ns) and each pixel dissipates 26 µW. Thanks to the use of multilevel offset correction, an effective offset spread calculated to the input is only 9 e- rms with the gain spread of 2 %. The count rate per pixel depends of the effective CSA feedback resistance and in the ultra fast mode a dead time of the front-end electronics is only 85 ns (paralyzable model).