Conference paper

A 10-phases Programmable Clock Generator for the Application in Control of SAR ADC Realized in the CMOS 130 nm Technology

R. Długosz, T. Talaśka (UTP Univ. of Science and Techn., Poland)

In this paper we present a 10-phases programmable clock generator for the application in control of Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC), realized in the CMOS 130~nm technology. The circuit provides 10 clock signals on separate terminals (sections). The programmable feature means that we can program the number of clock phases which are cyclically repeated. The circuit allows also to select which sections are used at the moment. For example, in case if only 6-phases are needed, we can obtain them on terminals 0-5, 1-6, ..., 4-9. This feature is important looking from the point of view the SAR ADC, in which corresponding branches can also be selected in the same way. The clock generator allows to control the width of the clock phases, which is also a useful feature.

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Receipt of papers:

March 15th, 2024

Notification of acceptance:

April 30th, 2024

Registration opening:

May 1st, 2024

Final paper versions:

May 15th, 2024