Conference paper

A New High-Speed and Low Power Synchronous Up/Down Counter

M. Ghasemzadeh (Urmia Univ., Iran)

A high speed and low power up/down counter is proposed in this paper with the ability of up and down counting at the same time. For this reason, straight forward circuit architecture is adopted for the counter. This counter has been simulated in TSMC 0.18µm CMOS process with 1.8 V as power supply. The post layout results show that an 8-bit resolution is feasible for the maximum operating frequency of 3.34 GHz with the power dissipation of 946 µW. The layout of the proposed counter occupies about 0.025mm2 of the chip area.

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Receipt of papers:

March 15th, 2021

Notification of acceptance:

May 11th, 2021

Registration opening:

May 17th, 2021

Final paper versions:

May 31th, 2021