Architectural Evaluation of Iterative and Unrolled AES-128 in 45 nm Using an Open-Source Flow

D. Santos, J. Cabacinho (NOVA School of Science and Techn., Portugal), J. Casaleiro (Lisbon School of Engineering, Portugal), L. Oliveira (NOVA School of Science and Techn., Portugal)

This paper presents a systematic architectural evaluation of iterative, partially unrolled and fully pipelined AES-128 cores synthesized using a fully open-source ASIC flow in 45 nm technology. Three design points are explored under identical synthesis conditions: a 10-cycle iterative architecture reusing a single round block, a 2-round partially unrolled implementation and a fully unrolled 10-stage 128-bit pipeline producing one block per clock cycle after pipeline fill. All designs were synthesized with Yosys and analyzed using OpenSTA and the Nangate 45 nm standard-cell library. The fully pipelined architecture achieves up to 881 MHz and 113 Gbps in post-synthesis timing analysis. To enable fair comparison with prior literature, silicon area was additionally normalized to 65 nm, allowing consistent throughputper-area evaluation across technology nodes. A composite-field 𝑮𝑭((𝟐𝟒)𝟐) S-Box variant is also implemented to quantify the impact of arithmetic structure on frequency, area and efficiency. All architectures were validated against NIST reference vectors, demonstrating that open-source design flows enable reproducible and consistent exploration of AES hardware trade-offs.