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Conference paper

Design of a Soft-processor for Educational Purposes

M. Heimowski, P. Buluk, A. Bruździak, J. Komoszewski, B. Pankiewicz (Gdansk Univ. of Techn., Poland)

Soft-processors commonly find use in FPGA-based systems as a way of introducing software-defined, re-programmable functionality into a fixed hardware design. The independence of a soft-processor from a specific hardware solution also makes this class of devices an attractive educational resource, allowing students to freely analyze, reconfigure and re-implement a complete microprocessor design. This article showcases the design considerations and implementation of a simple, RISC-like soft-processor core, acting as a demonstration platform for a variety of architectural concepts, while maintaining an approachable level of complexity, as well as not being limited by compatibility with specific programmable logic vendors.

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Receipt of papers:

March 15th, 2026

Notification of acceptance:

April 30th, 2026

Registration opening:

May 2nd, 2026

Final paper versions:

May 15th, 2026