A 400 fs Resolution Vernier TDC with Adaptive Voltage Scaling

D. Manuel (Univ. Nova de Lisboa, Portugal), L. Rodovalho, H. Gonçalves (Synopsys, Portugal), L. Oliveira (Univ. Nova de Lisboa, Portugal)

This paper proposes the development of a 3-bit Vernier TDC with a sub-ps time resolution to be used as a phase detector in a PLL. Furthermore, this work also implements an adaptive voltage scaling scheme by incorporating a regulator in conjunction with a PTAT current source to mitigate fluctuations in resolution across PVT conditions. Both components were implemented and simulated using a 16 nm FinFET technology node. The aforementioned system achieves an average time resolution of 400 fs with a maximum PVT variance of 52 fs, presenting a INL of 0.054 LSB, while consuming 1.46 mW of power and occupying a silicon area of 188 μm2.