RC Time-Constant Calibration Scheme Using a DPLL

J.P. Carvalho, N. Paulino (NOVA School of Science and Techn., Portugal), B. Nowacki (Renesas, Portugal)

This paper presents a mixed-signal calibration scheme for RC time constants. The calibration adjusts a programmable resistor array controlled by a 5-bit word inside a digitally controlled oscillator. Calibration is based on a DPLL locking mechanism, which generates the appropriate calibration digital code for given operating conditions. The calibration loop was evaluated across process, voltage and temperature (PVT) corners and Monte-Carlo simulations. The proposed architecture was implemented in 65 nm \textit{TSMC} technology, achieving a tuning accuracy ranging from -2.1\% to 1.6\% with an occupied area of 0.01 mm$^2$. The area of the circuit was estimated (140\% of the combined area of all components).