A Low-area, Digitally Controlled Low Dropout Regulator with Calibration Logic Optimized for RRAM Control

J. Ślubowski, A. Pawłowski, K. Sobolewski, K. Ber, T. Borejko (IMIO WUT, Poland), P. Wiśniewski (CEZAMAT, Poland), W. Pleskacz (IMIO WUT, Poland)

This work presents a low area, programmable on-chip Low Dropout (LDO) regulator. The proposed design utilizes a hybrid architecture with single pass FET output power transistor and multistage digital control logic placed in the feedback loop. Design is optimized for on-chip synthesis of voltages required for the forming, programming and readout of RRAM devices, especially in memory and security applications. The discussed version implements a 6-bit digital control word enabling 64 discrete voltage levels in a 0.2 - 4.0 V range making the architecture compatible with wide range of RRAM devices and applications.