The Impact of Chip Scaling on the Security of Data Storage in DRAM

J. Warmbier, M. Szymkowiak, P. Pawłowski (Poznan Univ. of Techn., Poland)

Modern memory subsystems are based on synchronous dynamic random-access memory (SDRAM), which has evolved into two main product families: double data rate (DDR) and low-power double data rate (LPDDR). The former is predominantly used in desktop and server systems, whereas the latter is primarily adopted in mobile devices and laptops. This work focuses on DDR5 and LPDDR5, which are prevalent in contemporary systems yet remain limited in the literature. Data stored in DRAM is volatile because the charge stored in capacitors leaks over time, eventually leading to data loss; therefore, periodic refresh operations are required every 32 ms or 64 ms according to industry standards. In this work, experiments were performed under thermally controlled conditions. The results show that data can be retained for approximately 8 s in LPDDR5 and 11.5 s in DDR5 under the evaluated conditions. They also indicate that the written data pattern affects data retention time as a consequence of continued technology scaling.