An Asynchronous Circuit for Pattern Comparison Based on Programmable Gates and Asynchronous Incrementers and Decrementers

M. Kolasa (Bydgoszcz Univ. of Science and Techn., Poland), M. Długosz (Poznan Univ. of Techn., Poland), T. Talaśka (Bydgoszcz Univ. of Science and Techn. and Gdansk Univ. of Techn., Poland), R. Długosz (Bydgoszcz Univ. of Science and Techn. and Aptiv Services, Poland)

Pattern comparison is one of the main operations in artificial intelligence systems. Such systems frequently rely on similarity measures such as Hamming distance. Efficient hardware implementation of such measures requires appropriate digital components capable of both bitwise comparison and difference accumulation. In this work, we present an application of a programmable digital logic gate driven by a 1-bit signal that can operate in either NAND or NOR mode in a circuit that allows for the Hamming distance computation. The programmable gate has been designed at the transistor level and enables efficient implementation of asynchronous increment and decrement structures, providing the basis for asynchronous hardware implementation of the pattern comparison block.