Realisation of Simple Logic Circuits Using a Quantum Processing Unit - A Case Study

M. Zubert, P. Duniec, K. Hałagan (Lodz Univ. of Techn., Poland)

This paper examines the feasibility of implementing selected classical logic circuits on a superconducting quantum processor architecture. A half-adder and an 8-bit Hamming SECDED (Single Error Correction, Double Error Detection) encoder were implemented using native gates and evaluated via noise-aware simulations based on the IBM Heron r2 quantum processor unit. The half-adder achieved functional and logical correctness with a state accuracy of 96.24%, indicating only moderate degradation under realistic noise conditions. In contrast, the significantly deeper SECDED encoder produced the ideal codeword in 73.45% of cases, while 26.55% of outcomes deviated from the expected result, including 11.82% classified as uncorrectable or ambiguous. Benchmarking results show that single-qubit gates are not the primary source of errors; instead, performance is limited by two-qubit CZ operations, circuit depth, qubit-pair non-uniformity, routing overhead, and limited readout-error mitigation. The results suggest that while simple logic circuits are feasible on current superconducting architectures, more advanced circuits may benefit from platforms with denser or more flexible connectivity.