Conference paper

Implementation of Addition and Subtraction Operations in Multiple Precision Arithmetic

K. Rudnicki (Brightelligence Inc., UK), T. Stefanski (Gdansk Univ. of Techn., Poland)

In this paper, we present a digital circuit of arithmetic unit implementing addition and subtraction operations in multiple-precision arithmetic (MPA). This adder-subtractor unit is a part of MPA coprocessor supporting and offloading the central processing unit (CPU) in computations requiring precision higher than 32/64 bits. Although addition and subtraction operations of two n-digit numbers require O(n) operations, the efficient implementation of these operations can provide valuable time-savings for the MPA coprocessor. Furthermore, MPA numbers are usually stored with the use of the sign-magnitude representation which is not so straightforward for addition/subtraction implementation as the two's complement representation. Our adder-subtractor unit is implemented using the very high speed integrated circuit hardware description language (VHDL) and benchmarked on Xilinx Artix-7 FPGA. The developed digital circuit of the MPA adder-subtractor works with integer numbers of precision varying in the range between 64 bits and 32 kbits with the limb size set to 64 bits. It can currently work with the clock frequency exceeding 450 MHz. For the developed implementation, the addition of two k-limb numbers takes 33+k clock cycles. Hence, the developed coprocessor is 1.7 times faster than a single core of modern i7 processor for precision set to 32704 bits.

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Receipt of papers:

February 29th, 2020

Notification of acceptance:

April 25th, 2020

Registration opening:

April 30th, 2020

Final paper versions:

May 15th, 2020