Conference paper

A 4.5 fJ/Conversion-step 10-bit 0.6V Asynchronous SAR ADC for Battery-free Miniature Sensor Nodes in 65nm CMOS

A. Dadashi, Y. Berg, O. Mirmotahari (Univ. Oslo, Norway)

This paper presents a 0.6-V energy-efficient 10-bit Asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with internal clock generator. Also a multiplexer is designed to serially transfer the output bits to outside the chip. A novel capacitive array also is proposed in this paper. The prototype is designed and fabricated in a 65-nm CMOS with a core size of 290 μm × 130 μm (0.0377 mm2). At 2.4 KS/s and Nyquist rate input, it consumes 4 nW at 0.6-V supply with an achieved signal-to-noise-and distortion ratio of 53.2 dB and a resulting figure of merit (FOM) of 4.5 fJ/conv.-step. Prototyped in a low-power 65 nm CMOS process, the ADC achieves an INL and DNL of 1.57 LSB and 0.95 LSB respectively at 0.6 V supply.

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Receipt of papers:

February 29th, 2020

Notification of acceptance:

April 25th, 2020

Registration opening:

April 30th, 2020

Final paper versions:

May 15th, 2020