Conference paper

Software Tool Aiding Analysis and Design of Low Power Parallel Prefix Adders

I. Brzozowski (AGH Univ. of Science and Techn., Poland)

In this paper a software tool aiding design of Parallel Prefix Adders is presented. It supports design of carry generation-propagation block by calculating a circuit activity and equivalent capacitance for requested input activity behavior. Thanks to graphical interface a user can test many possibilities in easy way by drawing a graph of propagation-generation block. Parameters are calculated and shown on the graph for all nodes. Finally after checking of the graph completeness the netlist of the adder is generated. The tool is useful when the designer, looking for the best solution, wants to analyze many adders structures for given input activity scenarios.

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Receipt of papers:

March 15th, 2021

Notification of acceptance:

May 11th, 2021

Registration opening:

May 17th, 2021

Final paper versions:

May 31th, 2021