Conference paper

SPAD Mixed-Quenching Circuit in 0.35-μm CMOS for Achieving a PDP of 39.2% at 854 nm

A. Dervic, H. Zimmermann (TU Wien, Austria)

This paper presents a fully-integrated optical sensor with SPAD and mixed quenching/resetting circuit with sensing stage based on a tunable-threshold inverter optimized for the standard 0.35-µm CMOS technology. The presented quencher features a controllable detection threshold voltage and an adjustable total dead time. The quenching circuit 5QC achieves 16.5 V excess bias voltage (five times the supply voltage). The dead time ranges from 7.5 ns to 51.5 ns, which corresponds to a saturation count rate range from 19.4 Mcps to 133.3 Mcps. The quencher is optimized for SPADs with a capacitance ranging from 50 fF up to 400 fF. Using our recently published measured photon detection probability (PDP) results and extrapolating them, a peak PDP of 75.6% at 652 nm and a PDP of 39.2% at 854 nm is estimated for VEX = 16.5 V. To the authors’ best knowledge, the presented PDP result has never been reached before for a fully-integrated SPAD sensor in standard CMOS technology.

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Receipt of papers:

March 15th, 2022

Notification of acceptance:

April 30th, 2022

Registration opening:

May 12th, 2022

Final paper versions:

May 20th, 2022