Conference paper

Comparative Analysis of CMOS Latch-Driver Circuits for Current-Steering Digital-to-Analog Converters

O. Morales Chacon, J. Wikner, A. Alvandpour (Linkoping Univ., Sweden), L. Siek (Nanyang Technological Univ., Singapore)

In this paper a comparative analysis of single- and dual-phase-clocked latch-driver circuits aimed at current-steering (CS) digital-to-analog converters (DACs) is presented. The design metrics of power consumption, propagation-, switching-delay and their product are considered. Also, an alternative latch-driver is proposed to sustain low-power consumption with short switching-delay. A 65 nm CMOS process is used and the results are obtained from post-layout simulations. In the analysis, dual-phase-clocked circuits consume about 2.4× more power consumption and report 5.9× shorter switching-delay with respect to the single-phase-clocked circuits. The proposed latch-driver consumes about 1.6× more power with maintained switching-delay as the dual-phase-clocked solutions, leading to a reduction in the power-delay product of 25% and the lowest power-switching-delay product within the supply range 0.8 to 1.2 V.

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Receipt of papers:

March 15th, 2022

Notification of acceptance:

April 30th, 2022

Registration opening:

May 12th, 2022

Final paper versions:

May 20th, 2022