Day 1: June 26th, 2025 (Thursday)
| Time | Room A |
| 09:00 |
Conference Opening
Chairmen: Prof. Wojciech Tylman and Prof. Andrzej Pfitzner
|
| 09:05 |
Plenary Session I
Chairman: Prof. Wojciech Tylman
Presentation Commemorating Life and Achievements of Prof. Andrzej Napieralski Mixed Mode: More than Analog and Digital Modern Challenges in Hardware Design |
| 10:50 | Coffee Break |
| 11:20 |
Session 1 (Part 1): Design of Integrated Circuits and Microsystems
Chairman: Prof. Andrzej Pfitzner
CMOS OTA for Detector Readout Electronics Integrator in the ALICE FIT Project Design and Optimization of OTA-C Filters with Shared CMFB and Output Stages: Performance, Power, and Area Analysis Design Considerations for Integrated SiGe BiCMOS Phase-Locked Loops in the Millimeter-Wave Band |
| 13:00 | Lunch |
| 14:00 |
Session 1 (Part 2): Design of Integrated Circuits and Microsystems
Chairman: Prof. Witold Pleskacz
Enhancing Test-Driven Development for Reconfigurable Hardware through High-Level Synthesis and Early-Stage Validation FSMLock: Sequential Logic Locking Case Study Recording Channel Parameters Influence Analysis on Time-Related X-ray Based Measurements in CMOS 40 nm |
| 19:00 | Welcome Party |
| Time | Room B |
| 10:50 | Coffee Break |
| 11:20 |
Session 2: Signal Processing
Chairman: Prof. Wojciech Tylman
Azure Kubernetes Service Design Principles in Machine Learning Systems High-Accuracy ECG Signal Acquisition Using a Power-Efficient 6-bit Level-Crossing ADC Low Voltage, High Power Electronic Load Design for FPGA Current Draw Reproducing Recurrent LSTM Neural Networks for Language Modelling and Speech Recognition |
| 13:00 | Lunch |
| 14:00 |
Session 3: Analysis and Modelling of ICs and Microsystems
Chairman: Prof. Alexander Kloes
Fractional Spurious Tones Analysis of the Space-Time Averaging PLL High-Level Modeling of RF Power Amplifiers and Antenna Arrays for Efficient Over-the-Air Power Combination in RF Transceivers Reliability Analyses of Ultra-Low Voltage Analog Spiking Neurons |
| 19:00 | Welcome Party |
| Time | Room C |
| 10:50 | Coffee Break |
| 11:20 |
Session 4: Power Electronics
Chairman: Prof. Witold Pleskacz
A Thermal Behavior of Lateral (VESTIC) BJTs on SOI Substrate Considerations on the Importance of Proper Modeling of Heat Transfer Coefficient Values Influence of the Cooling System on Characteristics of Power LEDs in COB Packages |
| 13:00 | Lunch |
| 14:00 |
Session 5: Embedded Systems
Chairman: Prof. Paweł Śniatała
A Survey and Practical Application of Ethernet-APL, PROFINET Network and HMI Comparative Survey Between Industrial Communication Protocols Applied in Hazardous Areas Analysis of Selected Cryptographic Algorithms for Data Transmission in Airborne Networks Matlab Simulations in Performance Analysis of Storage Area Networks |
| 19:00 | Welcome Party |
Day 2: June 27th, 2025 (Friday)
| Time | Room A |
| 09:00 |
Plenary Session II
Chairman: Prof. Andrzej Pfitzner
AI for Processors, Processors for AI: Going New Ways for Processor Architectures Electronic Control Systems for Ion Trap Quantum Computers |
| 10:00 |
Session 1 (Part 3): Design of Integrated Circuits and Microsystems
Chairman: Prof. Andrzej Pfitzner
Design of the Charge-Sampling Multiplying PLL in CMOS 40 nm Optimum Design of a Mostly-Digital Fleischer-Laker Switched-Capacitor Bilinear Bandpass Filter in Standard CMOS Technology Practical Implementation of Voltage-to-Current and Current-to-Voltage Converter in High Voltage SOI Technology |
| 11:00 | Coffee Break |
| 11:30 |
Session 1 (Part 4): Design of Integrated Circuits and Microsystems
Chairman: Prof. Wojciech Tylman
Implementation of a PLL Loop Circuit for Frequency Synthesis in 65 nm CMOS Technology SHA-256 Hash Generator in Verilog HDL SYNAPSE - A New Approach to Semi-automated Design of Ultra-low-power Application-specific Embedded Processors |
| 13:00 | Lunch |
| 14:00 | Tourist Activities |
| 19:00 | Conference Banquet & Closing Ceremony |
| Time | Room B |
| 10:00 |
Session 6 (Part 1): Artificial Intelligence in Electronic Systems
Chairman: Prof. Tomasz Stefański
Video-assisted Dentistry with Deep Neural Networks Application of Modified Particle Swarm Optimization Algorithm in FIR Filter Design Edge Computing of Human Poselet |
| 11:00 | Coffee Break |
| 11:30 |
Session 6 (Part 2): Artificial Intelligence in Electronic Systems
Chairman: Prof. Rafał Długosz
Anomaly Detection on the Edge: Comparison of Reconstruction and Classification Based Approaches Application of Dual-Q TQWT for Atrial Fibrillation Detection with Three-Layered Neural Network Design Flow for AI-driven Medical Systems Demonstrated through an Example in Dental Imaging Analysis Evaluating Device Variability in RRAM-Based Single- and Multi-Layer Perceptrons |
| 13:00 | Lunch |
| 14:00 | Tourist Activities |
| 19:00 | Conference Banquet & Closing Ceremony |
| Time | Room C |
| 10:00 | IEEE ED/EP Meeting: IEEE ED/EP Poland Section Technical Meeting |
| 11:00 | Coffee Break |
| 11:30 |
Special Session I: Advancing FOSS Compact Modelling: From OTF Transistors to Mott Memristors
Chairmen: Dr. Daniel Tomaszewski and Dr. Władysław Grabiński
A Generic Approach for Compact Modeling of Variability and Low-Frequency Noise in Organic Thin-Film Transistors Extraction of Open-Access-PDK Active Inductance Parameters with FOSS Tools Spiking Neurons Demystified by a Dynamical Model of Mott Memristors |
| 13:00 | Lunch |
| 14:00 | Tourist Activities |
| 19:00 | Conference Banquet & Closing Ceremony |
